Designing an Efficient Flash Translation
Flash memory is a linear device consisting of an array of blocks. The flash translation layer (FTL) is a software/firmware layer implemented inside a flash-based storage device to make the linear device act like a block-based device. This translation layer helps existing applications use flash-based storage devices without any modifications. The FTL receives logical read and write commands from the application and converts them to internal flash commands. The FTL also controls the logical-to-physical page mapping inside the storage device, which directly affects the read and write performance and cell wear-out problem. This mapping can be maintained at the page-level, block-level, or a hybrid combination of both block-level and page-level. Additional research is needed to design an efficient FTL that provides high performance with efficient use of space. A related problem is designing a wear-leveling algorithm that considers the limited number of block erasures permitted in each flash block. We have found one of the critical issues for designing efficient FTL and wear-leveling algorithms is how to identify Hot and Cold Data, which is data that will be updated in the near future and data that will not be updated for a long period of time, respectively.
|Nov 6, 2023||Devashish Purandare, Sam Schmidt, Ethan L. Miller, Designing an Efficient Flash Translation] [Designing systems for QLC flash]|
|Jan 10, 2022||Devashish Purandare, Pete Wilcox, Heiner Litz, Shel Finkelstein, Archival Storage] [Designing an Efficient Flash Translation] [Designing systems for QLC flash] [Shingled Disk] [Computational Storage]|
|Sep 7, 2015||Jehan-François Pâris, Darrell D. E. Long, Designing an Efficient Flash Translation]|
|Sep 9, 2014||Yan Li, Darrell D. E. Long, Designing an Efficient Flash Translation]|
Last modified 23 May 2019