Designing systems for QLC flash
Quad Level Cell (QLC) flash promises to make SSDs 33% cheaper. It has read and write performance which is close to other Multi Level Cell (MLC) technologies while offering more bits per cell. However, it comes with significant trade-offs for reliability and durability. This project aims to analyze and profile the behavior of QLC flash, and design systems which can ameliorate the limitations of QLC flash.
QLC flash can distinguish 16 levels of voltage in each cell, allowing 4 bits per cell. Each program/erase (PE) cycle wears down the cell allowing charge to leak. As QLC has 16 levels of voltage to distinguish, the tolerance to errors is much finer and can cause the cell to degrade much faster. The durability of QLC is expected to be a little over 100 PE cycles.
This project aims to design systems that can effectively utilize QLC flash. It will involve an analysis of the kinds of errors that occur in QLC, and details about their granularity, occurrence, and frequency. Based on this, schemes like erasure coding and error detection and correction codes can be used to address limitations of QLC flash.
The project will work on design and architecture of multi-level storage systems. The benefits offered by other types of flash memories can be used to offset limitations of QLC flash in reliability and durability. QLC will allow higher capacity SSDs which can replace disks, while offering better read/write performance. Addressing the limitations of QLC will allow us to make it a viable alternative for a variety of workloads.
Analysis of errors in QLC flash is in progress. The project is now active. We are working on identifying the role QLC can play in archival and industrial workloads.
|May 20, 2019||Designing systems for QLC flash]|
|Jun 14, 2018||Dev Purandare, Archival Storage] [Designing systems for QLC flash] [Tracing and Benchmarking] [Ultra-Large Scale Storage]|